DV Engineer

We are seeking a talented and motivated B.Tech/M.Tech graduate in Electrical Engineering (EE) or Electronics and Communication Engineering (ECE) to join our team as a Digital SoC Verification Engineer. Requirements 1-3 years of experience in digital SoC verification (bonus points if you have experience with processor-based SoCs ) Solid knowledge of SystemVerilog (SV), UVM, C, Perl, and Python Experience developing test plans and verification environments A quick learner with exceptional analytical skills Strong teamwork, communication, and interpersonal skills High motivation and a drive to succeed Responsibilities you ll be a key player in ensuring the quality of our chip designs by planning and strategizing effective verification strategies. This includes creating comprehensive verification plans for individual blocks and the entire chip, using tools like vPlanner. you ll leverage your expertise in SystemVerilog (SV) and UVM to verify blocks at both the module and system level, including netlist simulations. you ll be an expert in UVM-based verification methodologies, utilizing assertions, functional coverage, and formal verification to achieve verification goals. you ll collaborate closely with product development teams to refine and enhance existing verification methodologies. Familiarity with emulation platforms is a plus