Job Description
Setup and own Digital implementation flow
Work on hierarchical design and integration
Debug all digital design rule checks including DFT, apply design fixes to achieve high test quality
Implement Soc DFT strategy and architecture
Synthesis including DFT insertion (Scan and MBIST)
Timing constraint development, Logic equivalence check
DFT test pattern generation and debug
Position requirements
Bachelor or Masters degree in Electrical/Electronics/Computer science from a reputed institute
1-3 years of Industry experience
Very good understanding of digital logic design principles
RTL coding , simulation, debugging skills
Very good knowledge of Design for Test (DFT)
Good knowledge of ASIC implementation flow
Good verbal and written communication skills
