Job Description
Synthesis and Static timing analysis for high performance digital designs
Synthesis, LEC and STA flow setup, convergence, reviews
Timing constraint development, analysis, validation and debug
Timing, Noise, DRC (transition, capacitance) signoff across multi-mode, multi-corner
STA flow optimization
Work on design automation using TCL/Perl/Python
Position Requirements
BTech/MTech degree in Electrical/Electronics/Computer Engineering from a reputed institute
1-3 years of Industry experience
Hands on experience with the STA and Signoff of complex high speed SoC designs in cutting edge process technologies
Ability to develop complex timing constraints by working with designers
Familiar with digital flow design aspects RTL to GDS
Good expertise in tcl/perl/python scripts and automation on timing analysis tools
Good verbal and written communication skills
