Digital Design Engineer

Translate the design specification to an optimal micro-architecture for digital blocks RTL coding using Verilog and System Verilog Meet power, performance and area goals by micro-architecture optimization Block level Designer verification Work closely with DV team to develop test-plans Front end implementation - Lint/CDC , synthesis, Timing constraint development Work closely with DFT and PD teams for signoff Support Silicon validation Position requirements Bachelor or Masters degree in Electrical/Electronics/Computer science from a reputed institute 1-3 years of Industry experience Very good understanding of digital logic design principles RTL coding , simulation, debugging skills Good verbal and written communication skills Knowledge of Digital signal processing and processor architecture is a plus