. Responsible for and own all aspects of physical design and physical verification effort at a block level.
Worked on Netlist to GDSII at block level for multiple tapeouts
Expertise in hierarchical partitioning of block-level subsystems.
Hands on experience in implementing high performance cores, low power designs.
Nodes from 65nm, 40nm, 28nm, 20nm, 14nm, 10nm.
Experience in Power, Area with timing closure in parallel.
Flat timing closure of hierarchical sub systems with signoff STA
Block level floor planning, power planning and IR drop analysis.
Timing closure with Crosstalk and OCV (Advanced OCV)
CTS and clock tree constraints creation for meeting clock specifications
Scan chain reordering / Scan Chain repartitioning
Timing ECO and Functional ECO implementation at Netlist stage
Good knowledge of standard cell libraries - circuit design and cell layout.
Good understanding of STA, EM / IR and sign-off flows
High Performance Sub-Systems
Formal verification at various levels of design hierarchy with respect to golden RTL
Low Power Design (General Methodology, CPF, UPF)
TCL / PERL Scripting and creating quick procedures for solutions
Debugging and solution finding skills
Liaising with Team members and co-workers and Design team for delivery of the project and in finding solution
Top level implementation will be an added advantage
Develop, support and maintain physical design flows and methodologies.